
module axi_uart(
  /* verilator lint_off UNUSEDSIGNAL */
    input           clk,
    input           rst,
    output          axi_awready,
    input           axi_awvalid,
    input [31:0]    axi_awaddr,

    output          axi_wready,
    input           axi_wvalid,
    input [63:0]    axi_wdata,

    input           axi_bready,
    output          axi_bvalid,

    output          axi_arready,
    input           axi_arvalid,
    input [31:0]    axi_araddr,

    input           axi_rready,
    output          axi_rvalid,
    output  [63:0]  axi_rdata
  /* verilator lint_on UNUSEDSIGNAL */
);

wire ready = axi_bready & axi_rready;
logic [31:0] waddr;
reg_l #(32) waddr_r (.din(axi_awaddr), .dout(waddr), .load(axi_awready & axi_awvalid), .*);

wire axi_wfire = axi_wvalid & axi_wready;

logic [63:0] counter;

logic bvalid,rvalid;
logic [63:0] rdata;

assign axi_awready = ready;
assign axi_arready = ready;
assign axi_wready = ready;
assign axi_bvalid = bvalid;
assign axi_rvalid = rvalid;
assign axi_rdata = rdata;

int fd;
initial fd = $fopen("axi_uart.out","w");
always_ff@(posedge clk) begin
    if(rst) begin
        counter <= 'b0;
    end else if(axi_wfire & waddr == 'ha000_03f0) begin
        counter <= axi_wdata;
    end else begin
        counter <= counter + 'b1;
    end
    if(axi_wfire & waddr == 'ha000_03f8) begin
        $fwrite(fd,"%c",axi_wdata[7:0]);
    end
    if(rst) begin
        bvalid <= 'b0;
        rvalid <= 'b0;
    end else begin
        if(axi_bvalid & axi_bready) bvalid <= 'b0;
        if(axi_wvalid & axi_wready) bvalid <= 'b1;
        if(axi_rvalid & axi_rready) rvalid <= 'b0;
        if(axi_arvalid&axi_arready) rvalid <= 'b1;
    end
    if(axi_arvalid&axi_arready) begin
        rdata <= 'b0;
        if(axi_araddr == 'ha000_03f0) rdata <= counter;
    end
end



endmodule
